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APPLICATION NOTES
AVAILABLE
AN3 * AN7 * AN8 * AN15 * AN16 * AN25 * AN29 * AN30 * AN35 * AN36 * AN39 * AN56 * AN69
X24C44 256 Bit
X24C44
Serial Nonvolatile Static RAM
16 x 16 Bit
FEATURES
DESCRIPTION
The Xicor X24C44 is a serial 256 bit NOVRAM featuring a static RAM configured 16 x 16, overlaid bit-by-bit with a nonvolatile E2PROM array. The X24C44 is fabricated with Xicor's Advanced CMOS Floating Gate technology. The Xicor NOVRAM design allows data to be transferred between the two memory arrays by means of software commands or external hardware inputs. A store operation (RAM data to E2PROM) is completed in 5ms or less and a recall operation (E2PROM data to RAM) is completed in 2s or less. Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM and a minimum 1,000,000 store operations. Inherent data retention is specified to be greater than 100 years.
* * * *
* * * * * *
Advanced CMOS Version of Xicor's X2444 16 x 16 Organization Single 5 Volt Supply Ideal for use with Single Chip Microcomputers --Static Timing --Minimum I/O Interface --Serial Port Compatible (COPSTM, 8051) --Easily Interfaced to Microcontroller Ports Software and Hardware Control of Nonvolatile Functions Auto Recall on Power-Up TTL and CMOS Compatible Low Power Dissipation --Active Current: 10mA Maximum --Standby Current: 50A Maximum 8-Lead PDIP, Cerdip, and 8-Lead SOIC Packages High Reliability --Store Cycles: 1,000,000 --Data Retention: 100 Years
FUNCTIONAL DIAGRAM
NONVOLATILE 2 E PROM
ST O
STATIC RAM 256-BIT
EC
AL
L
R
E
ROW DECODE
CONTROL LOGIC
R
RECALL (6) STORE (7)
CE (1) DI (3) SK (2)
INSTRUCTION REGISTER
COLUMN DECODE
DO (4)
INSTRUCTION DECODE
4-BIT COUNTER
3832 FHD F01
COPS is a trademark of National Semiconductor Corp. (c) Xicor, Inc. 1991, 1995, 1996 Patents Pending 3832-1.5 6/19/96 T2/C1/D1 NS
1
Characteristics subject to change without notice
X24C44
PIN DESCRIPTIONS Chip Enable (CE) The Chip Enable input must be HIGH to enable all read/ write operations. CE must remain HIGH following a Read or Write command until the data transfer is complete. CE LOW places the X24C44 in the low power standby mode and resets the instruction register. Therefore, CE must be brought LOW after the completion of an operation in order to reset the instruction register in preparation for the next command. Serial Clock (SK) The Serial Clock input is used to clock all data into and out of the device. Data In (DI) Data In is the serial data input. Data Out (DO) Data Out is the serial data output. It is in the high impedance state except during data output cycles in response to a READ instruction. STORE STORE LOW will initiate an internal transfer of data from RAM to the E2PROM array. RECALL RECALL LOW will initiate an internal transfer of data from E2PROM to the RAM array. PIN NAMES Symbol CE SK DI DO RECALL STORE VCC VSS Description Chip Enable Serial Clock Serial Data In Serial Data Out Recall Input Store Input +5V Ground
3832 PGM T01
PIN CONFIGURATION
PDIP/CERDIP/SOIC CE SK DI DO 1 2 3 4 X24C44 8 7 6 5 VCC STORE RECALL VSS
3832 FHD F02.2
2
X24C44
DEVICE OPERATION The X24C44 contains an 8-bit instruction register. It is accessed via the DI input, with data being clocked in on the rising edge of SK. CE must be HIGH during the entire data transfer operation. Table 1. contains a list of the instructions and their operation codes. The most significant bit (MSB) of all instructions is a logic one (HIGH), bits 6 through 3 are either RAM address bits (A) or don't cares (X) and bits 2 through 0 are the operation codes. The X24C44 requires the instruction to be shifted in with the MSB first. After CE is HIGH, the X24C44 will not begin to interpret the data stream until a logic "1" has been shifted in on DI. Therefore, CE may be brought HIGH with SK running and DI LOW. DI must then go HIGH to indicate the start condition of an instruction before the X24C44 will begin any action. In addition, the SK clock is totally static. The user can completely stop the clock and data shifting will be stopped. Restarting the clock will resume shifting of data. RCL and RECALL Either a software RCL instruction or a LOW on the RECALL input will initiate a transfer of E2PROM data into RAM. This software or hardware recall operation sets an internal "previous recall" latch. This latch is reset upon power-up and must be intentionally set by the user to enable any write or store operations. Although a recall operation is performed upon power-up, the previous recall latch is not set by this operation. WRDS and WREN Internally the X24C44 contains a "write enable" latch. This latch must be set for either writes to the RAM or store Table 1. Instruction Set Instruction WRDS (Figure 3) STO (Figure 3) Reserved WRITE (Figure 2) WREN (Figure 3) RCL (Figure 3) READ (Figure 1)
X = Don't Care A = Address
operations to the E2PROM. The WREN instruction sets the latch and the WRDS instruction resets the latch, disabling both RAM writes and E2PROM stores, effectively protecting the nonvolatile data from corruption. The write enable latch is automatically reset on power-up. STO and STORE Either the software STO instruction or a LOW on the STORE input will initiate a transfer of data from RAM to E2PROM. In order to safeguard against unwanted store operations, the following conditions must be true: * STO instruction issued or STORE input is LOW. * The internal "write enable" latch must be set (WREN instruction issued). * The "previous recall" latch must be set (either a software or hardware recall operation). Once the store cycle is initiated, all other device functions are inhibited. Upon completion of the store cycle, the write enable latch is reset. Refer to Figure 4 for a state diagram description of enabling/disabling conditions for store operations. WRITE The WRITE instruction contains the 4-bit address of the word to be written. The write instruction is immediately followed by the 16-bit word to be written. CE must remain HIGH during the entire operation. CE must go LOW before the next rising edge of SK. If CE is brought LOW prematurely (after the instruction but before 16 bits of data are transferred), the instruction register will be reset and the data that was shifted-in will be written to RAM. If CE is kept HIGH for more than 24 SK clock cycles (8-bit instruction plus 16-bit data), the data already shifted-in will be overwritten.
Format, I2 I1 I0 1XXXX000 1XXXX001 1XXXX010 1AAAA011 1XXXX100 1XXXX101 1AAAA11X
Operation Reset Write Enable Latch (Disables Writes and Stores) Store RAM Data in E2PROM N/A Write Data into RAM Address AAAA Set Write Enable Latch (Enables Writes and Stores) Recall E2PROM Data into RAM Read Data from RAM Address AAAA
3832 PGM T13
3
X24C44
READ The READ instruction contains the 4-bit address of the word to be accessed. Unlike the other six instructions, I0 of the instruction word is a "don't care". This provides two advantages. In a design that ties both DI and DO together, the absence of an eighth bit in the instruction allows the host time to convert an I/O line from an output to an input. Secondly, it allows for valid data output during the ninth SK clock cycle. D0, the first bit output during a read operation, is truncated. That is, it is internally clocked by the falling edge of the eighth SK clock; whereas, all succeeding bits are clocked by the rising edge of SK (refer to Read Cycle Diagram). LOW POWER MODE When CE is LOW, non-critical internal devices are powered-down, placing the device in the standby power mode, thereby minimizing power consumption. SLEEP Because the X24C44 is a low power CMOS device, the SLEEP instruction implemented on the first generation NMOS device has been deleted. For systems converting from the X2444 to the X24C44 the software need not be changed; the instruction will be ignored. WRITE PROTECTION The X24C44 provides two software write protection mechanisms to prevent inadvertent stores of unknown data. Power-Up Condition Upon power-up the "write enable" latch is in the reset state, disabling any store operation. Unknown Data Store The "previous recall" latch must be set after power-up. It may be set only by performing a software or hardware recall operation, which assures that data in all RAM locations is valid. SYSTEM CONSIDERATIONS Power-Up Recall The X24C44 performs a power-up recall that transfers the E2PROM contents to the RAM array. Although the data may be read from the RAM array, this recall does not set the "previous recall" latch. During this power-up recall operation, all commands are ignored. Therefore, the host should delay any operations with the X24C44 a minimum of tPUR after VCC is stable. Power-Down Data Protection Because the X24C44 is a 5V only nonvolatile memory device it may be susceptible to inadvertent stores to the E2PROM array during power-down cycles. Power-up cycles are not a problem because the "previous recall" latch and "write enable" latch are reset, preventing any possible corruption of E2PROM data. Software Power-Down Protection If the STORE and RECALL pins are tied to VCC through a pull-up resistor and only software operations are performed to initiate stores, there is little likelihood of an inadvertent store. However, if these two lines are under microprocessor control, positive action should be employed to negate the possibility of these control lines bouncing and generating an unwanted store. The safest method is to issue the WRDS command after a write sequence and also following store operations. Note: an internal store may take up to 5ms; therefore, the host microprocessor should delay 5ms after initiating the store prior to issuing the WRDS command. Hardware Power-Down Protection (when the "write enable" latch and "previous recall" latch are not in the reset state): Holding either RECALL LOW, CE LOW or STORE HIGH during power-down will prevent an inadvertent store.
4
X24C44
Figure 1. RAM Read
CE
SK
1
2
3
4
5
6
7
8
9
10
11
12
22
23
24
DI
1
A
A
A
A
1
1
X*
HIGH Z DO *Bit 8 of Read Instructions is Don't Care
3832 FHD F07.1
D0
D1
D2
D3
D13
D14
D15
D0
Figure 2. RAM Write
CE
SK
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
DI
1
A
A
A
A
0
1
1
D0
D1
D2
D12
D13
D14
D15
3832 FHD F08.1
Figure 3. Non-Data Operations
CE
SK
1
2
3
4
5
6
7
8
DI
1
X
X
X
X
I2
I1
I0
3832 FHD F09.1
5
X24C44
Figure 4. X24C44 State Diagram
POWER ON
POWER-UP RECALL RAM READ ENABLED RAM READ
RCL COMMAND OR RECALL RAM READ ENABLED STO OR WRDS CMD OR STORE RAM READ & WRITE STORE ENABLED
3832 FHD F10.1
RAM READ
WREN COMMAND
RAM READ OR WRITE
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X24C44
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. -65C to +135C Storage Temperature ....................... -65C to +150C Voltage on any Pin with Respect to VSS ............................................ -1V to +7V D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. 300C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military Min. 0C -40C -55C Max. +70C +85C +125C
3832 PGM T02.1
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage X24C44
Limits 5V 10%
3832 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol lCC ISB1 ISB2 ILI ILO VlL(1) VIH(1) VOL VOH Parameter VCC Supply Current (TTL Inputs) VCC Standby Current (TTL Inputs) VCC Standby Current (CMOS Inputs) Input Load Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Min. Max. 10 1 50 10 10 0.8 VCC + 1 0.4 Units mA mA A A A V V V V Test Conditions SK = 0.4V/2.4V Levels @ 1MHz, DO = Open, All Other Inputs = VIH DO = Open, CE = VIL, All Other Inputs = VIH DO = Open, CE = VSS All Other Inputs = VCC - 0.3V VIN = VSS to VCC VOUT = VSS to VCC
-1 2 2.4
IOL = 4.2mA IOH = -2mA
3832 PGM T04.3
ENDURANCE AND DATA RETENTION Parameter Endurance Store Cycles Data Retention CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V Symbol COUT(2) CIN(2) Parameter Output Capacitance Input Capacitance Max. 8 6 Units pF pF Test Conditions VOUT = 0V VIN = 0V
3832 PGM T06.1
Min. 100,000 1,000,000 100
Units Data Changes Per Bit Store Cycles Years
3832 PGM T05
Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested.
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X24C44
EQUIVALENT A.C. LOAD CIRCUIT
5V
A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels
100pF
0V to 3V 10ns 1.5V
3832 PGM T07.1
919 OUTPUT 497
3832 FHD F11
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Read and Write Cycle Limits Symbol FSK(3) tSKH tSKL tDS tDH tPD1 tPD tZ tCES tCEH tCDS POWER-UP TIMING Symbol tPUR(4) tPUW(4) Parameter Power-up to Read Operation Power-up to Write or Store Operation Max. 200 5 Units s ms
3832 PGM T09
Parameter SK Frequency SK Positive Pulse Width SK Negative Pulse Width Data Setup Time Data Hold Time SK to Data Bit 0 Valid SK to Data Valid Chip Enable to Output High Z Chip Enable Setup Chip Enable Hold Chip Deselect
Min. 400 400 400 80
Max. 1
Units MHz ns ns ns ns ns ns s ns ns ns
3832 PGM T08.1
375 375 1 800 350 800
Notes: (3) SK rise and fall times must be less than 50ns. (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
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X24C44
Write Cycle
1/FSK SK CYCLE # SK x tCES CE tDS DI
3832 FHD F03
tSKH 1
tSKL 2 n tCEH tCDS
tDH
Read Cycle
SK CYCLE # 6 SK 7 8 9 10 n
VIH CE tPD
DI
I2
I1
DON'T CARE tPD1 tZ D0 D1 Dn HIGH Z
DO
HIGH Z
3832 FHD F04
9
X24C44
NONVOLATILE OPERATIONS Software Instruction NOP(5) RCL NOP(5) STO Write Enable Latch State X X SET SET Previous Recall Latch State X X SET SET
3832 PGM T10
Operation Hardware Recall Software Recall Hardware Store Software Store
STORE 1 1 0 1
RECALL 0 1 1 1
ARRAY RECALL LIMITS Symbol tRCC tRCP tRCZ Parameter Recall Cycle Time Recall Pulse Width(6) Recall to Output in High Z Min. 2 500 500 Max. Units s ns ns
3832 PGM T11
Recall Timing
tRCC tRCP RECALL tRCZ DO HIGH Z
3832 FHD F05
Notes: (5) NOP designates when the X24C44 is not currently executing an instruction. (6) Recall rise time must be <10s.
10
X24C44
STORE CYCLE LIMITS Symbol tST tSTP tZ VCC Store Timing Parameter Store Time Store Pulse Width CE to Output in High Z Store Inhibit Min. 200 1 3 Typ.(7) 2 Max. 5 Units ms ns s V
3832 PGM T12
CE tST tSTP STORE
tZ DO HIGH Z
3832 FHD F06
Note:
(7) Typical values are for TA = 25C and nominal supply voltage.
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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X24C44
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92) 0.360 (9.14)
0.092 (2.34) DIA. NOM.
0.255 (6.47) 0.245 (6.22)
PIN 1 INDEX PIN 1 0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51)
HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE 0.150 (3.81) 0.125 (3.18)
0.140 (3.56) 0.130 (3.30)
0.020 (0.51) 0.015 (0.38) 0.062 (1.57) 0.058 (1.47) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
0.015 (0.38) MAX.
0.325 (8.25) 0.300 (7.62)
TYP. 0.010 (0.25)
0 15
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F01
12
X24C44
PACKAGING INFORMATION
8-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
0.405 (10.29) --
0.310 (7.87) 0.220 (5.59)
PIN 1 0.300 (7.62) REF.
0.005 (0.13) MIN. 0.055 (1.40) MAX.
SEATING PLANE
0.200 (5.08) 0.140 (3.56)
0.150 (3.81) MIN.
0.200 (5.08) 0.125 (3.18)
0.060 (1.52) 0.015 (0.38) 0.065 (1.65) 0.038 (0.97) TYP. 0.060 (1.52) 0.023 (0.58) 0.014 (0.36) TYP. 0.017 (0.43)
0.110 (2.79) 0.090 (2.29) TYP. 0.100 (2.54)
0.320 (8.13) 0.290 (7.37) TYP. 0.311 (7.90)
0.015 (0.38) 0.008 (0.20)
0 15
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F05
13
X24C44
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) X 45 0.020 (0.50)
0.050" TYPICAL
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" TYPICAL
FOOTPRINT
0.030" TYPICAL 8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
14
X24C44
ORDERING INFORMATION
X24C44 Device
P
T
-V VCC Limits Blank = 5V 10% Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C M = Military = -55C to +125C Package P = 8-Lead Plastic DIP D = 8-Lead Ceramic DIP S = 8-Lead SOIC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness.
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